Field
In one aspect, the following relates to microprocessor architecture, and in one more particular aspect, to approaches to encoding instructions in machine code to be decoded within a microprocessor.
Related Art
An architecture of a microprocessor pertains to a set of instructions that can be handled by the microprocessor, and what these instructions cause the microprocessor to do. Architectures of microprocessors can be categorized according to a variety of characteristics. One major characteristic is whether the instruction set is considered “complex” or of “reduced complexity”. Traditionally, the terms Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC) respectively were used to refer to such architectures. Now, some modern processor architectures have characteristics that were traditionally associated with only CISC or RISC architectures. In practicality, a major distinction of meaning between RISC and CISC architecture is whether arithmetic instructions perform memory operations.
A RISC instruction set may require that all instructions be exactly the same number of bits (e.g., 32 bits). Also, these bits may be required to be allocated accordingly to a limited set of formats. For example, all operation codes of each instruction may be required to be the same number of bits (e.g., 6). This implies that up to 2^6 (64) unique instructions could be provided in such an architecture. In some cases, a main operation code may specify a type of instruction, and some number of bits may be used as a function identifier, which distinguishes between different variants of such instruction (e.g., all addition instructions may have the same 6-digit main operation code identifier, but each different type of add instruction, such as an add that ignores overflow and an add that traps on overflow).
Remaining bits (aside from the “operation code” bits) can be allocated according to identifying source operands, a destination of a result, or constants to be used during execution of the operation identified by the “operation code” bits). For example, an arithmetic operation may use 6 bits for an operation code, another 6 bits for a function code (individual and collectively, as relevant from context, the “operation code” bits), and then identify one destination and two source registers using 5 bits each. Even though a RISC architecture may require that all instructions be the same length and use the same storage (e.g., 32 bits), not every instruction may require all bits to be populated.